By Chenxin Zhang, Liang Liu, Viktor Öwall
This ebook makes a speciality of domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform that is versatile adequate to aid a number of criteria, a number of modes, and a number of algorithms. The content material is multi-disciplinary, masking components of instant communique, computing structure, and circuit layout. The platform defined presents real-time processing strength with average implementation price, attaining balanced trade-offs between flexibility, functionality, and bills. The authors talk about effective layout equipment for instant communique processing systems, from either an set of rules and structure layout viewpoint. insurance additionally contains computing structures for various instant applied sciences and criteria, together with MIMO, OFDM, monstrous MIMO, DVB, WLAN, LTE/LTE-A, and 5G.
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Additional info for Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing: From Algorithm to Architecture
Moreover, the implicit load-store operations lead to a compact code size, and make the memory operations possible in all instructions. Enhanced functionalities for digital signal processing include multiply-accumulate, radix-2 butterfly, and data swap. To reduce control overhead in computationally intensive inner loops, the GPC includes a zero-delay Inner loop controller (ILC). The ILC comprises a special set of registers that are used to store program loop count and return address. During program execution, the loop operation is indicated by an end-of-loop flag annotated in the last loop instruction.
Easy data sharing: The separation of memory from processing cells significantly simplifies data sharing, as memory cells can be shared by multiple processors without physically transferring data. Memory coherence is preserved by allowing direct data transfers between memory cells without involving processors. • Flexible memory usage: Memory cells can be individually configured to provide different access patterns, such as First in first out (FIFO), stack, and random access. , bit-reversal in FFT/IFFT.
Additionally, in conjunction with the tilebased architecture, the adopted NoC intrinsically supports Globally asynchronous locally synchronous (GALS) network construction. For example, synchronous transfers are performed within each tile and the global network (together with additional asynchronous FIFOs) is used to bridge between different clock domains. To connect RCs to the local and global network, adapters are used as a bridge between high level communication interfaces employed by RCs and network specific interfaces implemented in the NoC.