By Steve Leibson
Microprocessor cores used for SOC layout are the direct descendents of Intel's unique 4004 microprocessor. simply as packaged microprocessor ICs range extensively of their attributes, so do microprocessors packaged as IP cores. even though, SOC designers nonetheless examine and choose processor cores the way in which they formerly in comparison and chosen packaged microprocessor ICs. the large challenge with this feature procedure is that it assumes that the legislation of the microprocessor universe have remained unchanged for many years. This assumption isn't any longer valid.
Processor cores for SOC designs may be way more plastic than microprocessor ICs for board-level procedure designs. Shaping those cores for particular purposes produces far better processor potency and masses reduce process clock premiums. jointly, Tensilica's Xtensa and Diamond processor cores represent a relations of software-compatible microprocessors protecting a really huge functionality variety from basic keep watch over processors, to DSPs, to 3-way superscalar processors. but all of those processors use a similar software-development instruments in order that programmers accustomed to one processor within the relatives can simply swap to another.
This e-book emphasizes a processor-centric MPSOC (multiple-processor SOC) layout type formed by way of the realities of the 21st-century and nanometer silicon. It advocates the project of initiatives to firmware-controlled processors every time attainable to maximise SOC flexibility, reduce strength dissipation, decrease the scale and variety of hand-built good judgment blocks, slash the linked verification attempt, and reduce the general layout chance.
· a vital, no-nonsense advisor to the layout of 21st-century mega-gate SOCs utilizing nanometer silicon.
· Discusses present day key matters affecting SOC layout, in response to author's a long time of private event in constructing huge electronic structures as a layout engineer whereas operating at Hewlett-Packard's computer machine department and at EDA pc pioneer Cadnetix, and masking such themes as an award-winning expertise journalist and editor-in-chief for EDN journal and the Microprocessor Report.
· Explores conventionally authorised barriers and perceived limits of processor-based approach layout after which explodes those synthetic constraints via a clean outlook on and dialogue of the detailed talents of processor cores designed particularly for SOC design.
· Thorough exploration of the evolution of processors and processor cores used for ASIC and SOC layout with a glance at the place the has come from, and the place it really is going.
· Easy-to-understand motives of the features of configurable and extensible processor cores via a close exam of Tensilica's configurable, extensible Xtensa processor center and 6 pre-configured Diamond cores.
· the main complete evaluate on hand of the sensible features of configuring and utilizing a number of processor cores to accomplish very tough and bold SOC cost, functionality, and tool layout pursuits.
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Extra resources for Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores
7 Mondiale digital radio decoder. Systems that perform digital decoding and encoding, encryption and decryption, and other data-transformation algorithms are optimally organized or configured when the system block diagram matches the problem at hand. It is our familiarity with 30 years of microprocessorbased system design that starts us thinking along the lines of force-fitting task-specific architectural structures to traditional, bus-based microprocessor systems. 9, which shows the mapping of a set-top box system design into a traditional bus-based microprocessor system as it appeared in Chapter 4 of the book Surviving the SOC Revolution: A Guide to Platform-Based Design.
14 A CLOSER LOOKAT 21st-CENTURY PROCESSOR CORES FOR SOC DESIGN Microprocessor cores used for SOC design are the direct descendents of Intel's original 4004 microprocessor. They are all software-driven, storedprogram machines with bus interconnections. Just as packaged microprocessor ICs vary widely in their attributes, so do microprocessors packaged as IP cores. Microprocessor cores vary in architecture, word width, performance characteristics, n u m b e r and width of buses, cache interfaces, local m e m o r y interfaces, and so on.
Unlike most other processor cores available to SOC designers, the Xtensa core can be tuned to a very wide range of applications through the use of a u t o m a t e d tools and a processor generator that produce correct-by-construction RTL for the processor and an automatically tailored set of software-development tools for the tuned processor. The a u t o m a t e d generation of processor and tool set takes an h o u r or so. Thus the Xtensa processor ISA and its associated processor generator constitute an SOC-design tool that has been tailored from the start to create application-specific instruction-set processors (ASIPs).