By Gary D. Hachtel
Logic Synthesis and Verification Algorithms is a textbook designed for classes on VLSI good judgment Synthesis and Verification, layout Automation, CAD and complex point discrete arithmetic. It additionally serves as a easy reference paintings in layout automation for either pros and scholars.
Logic Synthesis and Verification Algorithms is set the theoretical underpinnings of VLSI (Very huge Scale built-in Circuits). It combines and integrates smooth advancements in common sense synthesis and formal verification with the extra conventional subject of Switching and Finite Automata concept. The e-book additionally presents historical past fabric on Boolean algebra and discrete arithmetic.
a different characteristic of this article is the massive selection of solved difficulties.
during the textual content the algorithms coated are the topic of 1 or extra difficulties in response to using on hand synthesis programs.