By Edwin R Coover
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Extra info for ATM switches
In today’s electronics milieu, silicon and memories and buses offer, at a given time, certain price/performance ranges. Very high performance is available only at very high cost. As consequence, one tries to create a product where high performance is achieved by a combination of marketplace components and clever design. The most common of these design tricks is parallel processing. Most are familiar with the concept of a bucket brigade, where buckets are handed back and forth along a single line.
Nonetheless, most usually it is the data link layer (ISO 2) with its cyclical redundancy check (CRC) that occasions these retransmissions. Usually it is invisible to the user. " Note, too, that present day error control is usually based on a link or portion of an end-to-end connection. One is familiar with the party game where some nonsense phrase is successively whispered from one guest to another. After very few transmission over an error-prone link (guests whispering), the phrase, whatever its initial understandability, is reduced to gibberish.
In ATM terms, the size of the bucket determines the cell delay variation tolerance (CDVT); the leak rate is the peak cell rate (PCR). 3. Explicit forward congestion indication (EFCI) is a cell header setting that may be examined by the destination end system. Its highway analogy is the freeway signs that warn motorists of impending delays and possible alternative routes. The highway parallel is particularly apt because the ATM switch, like the tired motorist, may choose to do nothing. EFCI is optional for CBR, both kinds of VBR and UBR; only in ABR is the end system obligated to do anything upon receiving the EFCI.